1. Field of the Invention
This invention is related to the field of integrated circuits and, more specifically, to recovering bit lines in a memory array.
2. Description of the Related Art
Integrated circuits may include embedded memory such as static random access memory (SRAM). Some integrated circuits may include only SRAM (e.g. SRAM chips designed for attachment to a circuit board with other integrated circuits). Other integrated circuits may include SRAM to store data used by logic circuitry also integrated into the integrated circuit.
Typical SRAM memory arrays include a plurality of memory cells coupled to a pair of bit lines used to access the memory cells. Generally, the bit lines are precharged (e.g. to the supply voltage) to prepare for a read/write operation. Multiple sets of memory cells coupled to different pairs of bit lines are used to provide a multiple bit input/output “word” of the memory array.
A read operation typically includes selecting one of the memory cells to output its stored bit, and the selected memory cell discharging one of the pair of bit lines based on the value of the bit stored in the memory cell. A sense amplifier (senseamp) circuit senses the differential between the voltages on the bit lines and amplifies the differential to output the bit from the memory array (either as a single bit or a differential pair with full signal swing). The memory array is designed such that the bit line is not fully discharged for a read operation. Subsequent to the senseamp sensing the bit lines, the bit lines are precharged to prepare for the next operation.
A write operation typically includes selecting one of the memory cells to be written, and driving the bit lines to write the bit into the selected memory cell. Since the bit lines are precharged prior to the start of the write operation, one of the bit lines is discharged based on the bit being written. Typically, the bit line is fully discharged (or almost fully discharged) for a write operation. The bit lines are subsequently precharged again to prepare for the next operation.
Since the discharge of a bit line for a read operation differs from that of a write operation, the current capability of the precharge circuits for each operation may differ. For most memory arrays, a large number of bit line pairs are present and thus the precharge control signals that cause the precharge drive a large number of precharge circuits. The capacitive load on the precharge control signals is proportional to the current capability of the precharge circuits, and thus the power dissipated in driving the precharge control signals is also proportional to the current capability. Accordingly, many memory arrays provide two precharge circuits for each bit line. One of the precharge circuits is designed to precharge the bit lines after a read operation, and thus has a relatively low current capability since the circuit need not be able to precharge all the way from ground to the supply voltage. Thus, less power is dissipated when a read operation is performed. Both precharge circuits are activated after a write operation, and the combination is designed to precharge a fully discharged bit line (e.g. from ground to the supply voltage).
Additionally, many integrated circuits may permit the clock or clocks in the integrated circuit to be stopped for a period of time without loss of state. For example, the clocks may be stopped for test purposes (e.g. to read the state of the integrated circuit or to change the state). The clocks may also be stopped for power management purposes.
While stopping the clocks is supposed to avoid a loss of state, if the clocks are stopped during a read operation prior to a precharge, the bit line may continue to discharge. If the clock is stopped for long enough, the bit line may discharge to a voltage that is lower than the precharge circuit is able to recover. When the clock starts again, the state of the integrated circuit indicates that a read was in progress and the read precharge circuit is activated. An incomplete precharge may thus occur.